1. Field of the Invention
The present invention generally relates to a program counter for an instruction prefetch device in an arithmetic processor of stored program type and, more particularly, to a device for generating an instruction address for an instruction to be executed subsequently.
2. Description of the Prior Art
An arithmetic processor of stored program type performs arithmetic processes by storing instructions in a storage device, reading the instructions from the storage device and executing the instructions in sequence. A program counter is a mechanism which obtains, in the arithmetic processor of stored program type, an address of an instruction to be executed next by adding a size (typically in bytes) of an instruction which is currently being executed to an address of the instruction, without describing, during execution of the current instruction, the address of the instruction to be executed next. Further, a prefetch circuit is a mechanism for enabling effective use of an interface between an arithmetic processor and an external device. In the stored program type arithmetic processor having a program counter, since instructions are executed in ascending address, a prefetch of instruction is possible when there is no conflict in an interface between the arithmetic processor and an external device.
The arithmetic processor of stored program type takes instructions and data therein through the external interfaces. When there is only one set of the external interfaces, which includes an address bus and a data bus, a data access and an instruction access share the interfaces. Therefore, during data access, the external interfaces are occupied. As a result, an instruction fetch, which is a read-in cycle of the instruction utilizing the external interfaces, is impossible. Where the external interfaces are occupied, an execution of a pipelined staging of the instruction fetch becomes possible by prefetching.
Whereas the program counter is incremented every instruction by the number of bytes of the instruction, a prefetch counter is incremented by a data size which can be handled by the external interfaces at once. The instruction size depends upon the kind of instruction and is typically one byte, two bytes, three bytes or four bytes, etc., and the data size corresponds to a size of the external interface and is usually two or four bytes. Therefore, values by which the program counter and the prefetch counter are incremented are not always identical.
The prefetch mechanism usually has a first-in, first-out (FIFO) buffer register. The FIFO register operates to output data in the order in which the data was originally input to the register. The prefetch address is counted in ascending order to generate addresses of instructions written in the FIFO buffer register in sequence. A memory is referenced with the prefetch addresses, and successive regions thereof are read out to the FIFO buffer. The FIFO buffer register also has an instruction align mechanism in which a stream of instructions in the buffer is divided to instruction units which are sent to an execution unit. The prefetch mechanism reads in the FIFO buffer register as large a number of instructions as possible so long as the external interfaces can be utilized, until the buffer register becomes full. When the FIFO buffer register becomes full, the instruction read-in cycle from the external bus interfaces is terminated.
The instruction address is an address of an instruction sent to the execution unit from the FIFO buffer register and is generated by an instruction address generation mechanism. The instruction address generator generates a value which is a sum of a current instruction address and a size of an instruction transmitted from the buffer register to the execution unit. Therefore, it is usual that the prefetch address generator circuit and the instruction address generator circuit operate independently to create an address to be prefetched next and an address of an instruction to be executed next. To this end, an adder for the prefetch address and an adder for creation of the instruction address are required, each having the same address bit width. If the whole mechanism were to be constituted as an integrated circuit, the adders would occupy a large area thereof. It is therefore highly desirable to realize the same functions while minimizing the size of the integrated circuit in which the prefetch mechanism is implemented.